Name
Abstract | ||
|---|---|---|
Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often consumed by on-chip caches, thus important research has focused on reducing energy consumption in these structures. To enhance performance, on-chip caches are being deployed with a high associativity degree. Consequently, accessing concurrently all the ways in the cache set is costly in terms of energy. This paper presents the PS-Cache architecture, an energy-efficient cache design that reduces the number of accessed ways without hurting the performance. The PS-Cache takes advantage of the private-shared knowledge of the referenced block to reduce energy by accessing only those ways holding the kind of block looked up. Experimental results show that, on average, the PS-Cache architecture can reduce the dynamic energy consumption of L1 and L2 caches by $$22$$22 and $$40\\,\\%$$40%, respectively. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/s11227-014-1288-5 | The Journal of Supercomputing |
Keywords | DocType | Volume |
Chip multiprocessors,Cache memories,Power consumption,Multithreaded applications | Conference | 71 |
Issue | ISSN | Citations |
1 | 0920-8542 | 2 |
PageRank | References | Authors |
0.36 | 26 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joan Josep Valls | 1 | 2 | 0.36 |
| Alberto Ros | 2 | 384 | 32.60 |
| Julio Sahuquillo | 3 | 420 | 53.71 |
| María Engracia Gómez | 4 | 149 | 17.48 |