| Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8. | 1 | 0.35 | 2020 |
| FOS: a low-power cache organization for multicores | 0 | 0.34 | 2019 |
| Modeling and analysis of the performance of exascale photonic networks. | 0 | 0.34 | 2019 |
| Efficient selective multicore prefetching under limited memory bandwidth. | 0 | 0.34 | 2018 |
| Workload Characterization for Exascale Computing Networks | 0 | 0.34 | 2018 |
| TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction. | 1 | 0.35 | 2018 |
| Modeling a Photonic Network for Exascale Computing | 1 | 0.40 | 2017 |
| Application Clustering Policies to Address System Fairness with Intel’s Cache Allocation Technology | 2 | 0.36 | 2017 |
| A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches. | 0 | 0.34 | 2017 |
| TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. | 2 | 0.36 | 2017 |
| A fault-tolerant routing strategy for k-ary n-direct s-indirect topologies based on intermediate nodes. | 0 | 0.34 | 2017 |
| XOR-based HoL-blocking reduction routing mechanisms for direct networks. | 0 | 0.34 | 2017 |
| A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies. | 1 | 0.41 | 2017 |
| A Directory Cache with Dynamic Private-Shared Partitioning | 0 | 0.34 | 2016 |
| A New Fault-Tolerant Routing Methodology for KNS Topologies. | 0 | 0.34 | 2016 |
| Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness. | 0 | 0.34 | 2016 |
| A Simple Activation/Deactivation Prefetching Scheme for Chip Multiprocessors | 1 | 0.35 | 2016 |
| The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks. | 5 | 0.47 | 2016 |
| TokenTLB: A Token-Based Page Classification Approach. | 5 | 0.40 | 2016 |
| A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies. | 0 | 0.34 | 2015 |
| Methodologies and Performance Metrics to Evaluate Multiprogram Workloads | 1 | 0.36 | 2015 |
| Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads | 0 | 0.34 | 2015 |
| Bringing real processors to labs | 0 | 0.34 | 2015 |
| Speeding-up the fault-tolerance analysis of interconnection networks | 0 | 0.34 | 2015 |
| PS directory: a scalable multilevel directory cache for CMPs | 2 | 0.40 | 2015 |
| A Research-Oriented Course on Advanced Multicore Architecture | 0 | 0.34 | 2015 |
| The Tag Filter Cache: An Energy-Efficient Approach | 1 | 0.35 | 2015 |
| Exploiting Parallelization on Address Translation: Shared Page Walk Cache. | 1 | 0.34 | 2013 |
| PS-Cache: an energy-efficient cache design for chip multiprocessors | 2 | 0.36 | 2013 |
| Deterministic Routing With Hol-Blocking-Awareness For Direct Topologies | 0 | 0.34 | 2013 |
| How to reduce packet dropping in a bufferless NoC | 1 | 0.36 | 2011 |
| EMC2: Extending Magny-Cours coherence for large-scale servers. | 0 | 0.34 | 2010 |
| Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network | 4 | 0.60 | 2008 |
| Reducing Packet Dropping in a Bufferless NoC | 27 | 1.12 | 2008 |
| Deterministic versus Adaptive Routing in Fat-Trees | 77 | 3.00 | 2007 |
| An efficient fault-tolerant routing methodology for fat-tree interconnection networks | 7 | 0.56 | 2007 |
| An Efficient Fault-Tolerant Routing Strategy for Tori and Meshes. | 0 | 0.34 | 2006 |
| A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes | 7 | 0.49 | 2004 |
