Name
Abstract | ||
|---|---|---|
The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCAD.2010.2049051 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
embedded nonvolatile memory,nand flash memory,built-in redundancy analysis,built-in self-repair (BISR),system in package,random-access storage,system-in-package,built-in self-repair schemes,deep submicrometer integrated circuit manufacturing technology,memory repair,yield,NAND flash memory,nor flash memory,2-d redundancy architecture,on-chip repair,redundancy architecture,bisr scheme,system-on-chip,flash memory,built-in self test,built-in self-test,page-mode operation,2D redundancy architecture,redundancy analysis,memory product,defective memory,Built-in redundancy analysis (BIRA),embedded memory,built-in self-repair scheme,redundancy analysis algorithm,flash memories | Journal | 29 |
Issue | ISSN | Citations |
8 | 0278-0070 | 7 |
PageRank | References | Authors |
0.69 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu-Ying Hsiao | 1 | 41 | 3.48 |
| Chao-Hsun Chen | 2 | 35 | 4.80 |
| Wu, Cheng-Wen | 3 | 1843 | 170.44 |