Name
Abstract | ||
|---|---|---|
A new solution to implement efficient switched-capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35−µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1002/cta.749 | I. J. Circuit Theory and Applications |
Keywords | Field | DocType |
classical sc integrator topology,charge transfer phase,proposed circuit,integrator speed,new solution,proposed scheme,new efficient sc integrator,capacitive feedback network,high-speed low-power application,john wiley,proposed configuration,proposed integrator,switched capacitor circuits,operational amplifiers,settling time | Power budget,Control theory,Integrator,CMOS,Switched capacitor,Electronic engineering,Op amp integrator,Passive integrator circuit,Mathematics,Integrating ADC,Operational amplifier | Journal |
Volume | Issue | ISSN |
40 | 8 | 0098-9886 |
Citations | PageRank | References |
2 | 0.40 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. A. Amoroso | 1 | 6 | 3.70 |
| A. Pugliese | 2 | 115 | 12.90 |
| Gregorio Cappuccino | 3 | 36 | 10.11 |