Name
Abstract | ||
|---|---|---|
This paper presents several challenges and solutions in designing an efficient Message Passing Interface (MPI) implementation for embedded FPGA applications. Popular MPI implementations are designed for general-purpose computers which have significantly different properties and trade-offs than embedded platforms. Our work focuses on two types of interactions that are not present in typical MPI implementations. First, a number of improvements designed to accelerate software-hardware interactions are introduced, including a Direct Memory Access (DMA) engine with MPI functionality; the use of non-interrupting, non-blocking messages; and a proposed function, called MPI_Coalesce, to reduce the function call overhead from a series of sequential messages. These improvements resulted in a speed-up of 5-fold compared to an embedded software-only MPI implementation. Next, a novel dataflow message passing model is presented for hardware-hardware interactions to overcome the limitations of atomic messages, allowing hardware engines to communicate and compute simultaneously. This dataflow model provides a natural method for hardware designers to build high performance, MPI systems. Finally, two hardware cores, Tee cores and message watchdog timers, are introduced to provide a transparent method of debugging hardware MPI designs. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/FPT.2009.5377688 | Sydney, NSW |
Keywords | Field | DocType |
embedded systems,field programmable gate arrays,message passing,MPI_Coalesce,dataflow message passing model,dataflow model,direct memory access,embedded FPGA application,embedded MPI functionality,embedded platform,field programmable gate arrays,hardware designers,hardware-based processing nodes,hardware-hardware interactions,message passing interface,software-hardware interaction | Subroutine,Computer science,Implementation,Real-time computing,Message Passing Interface,Dataflow,Direct memory access,Computer hardware,Message passing,Computer architecture,Parallel computing,Field-programmable gate array,Debugging,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-4377-2 | 1 | 0.42 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Le Ly | 1 | 34 | 2.38 |
| Manuel Saldaña | 2 | 62 | 5.96 |
| Paul Chow | 3 | 868 | 119.97 |