Name
Abstract | ||
|---|---|---|
This paper presents results concerning the design and testing of a fast network chip (the MP1) for parallel computers. We briefly introduce the theoretical results on which the MP1 chip design was based and describe its architecture. The chip has been fabricated and tested in small prototype system. Based on parameters measured using this prototype and a simulator implemented at the logic level we have been able to accurately model the performance of larger networks based on this chip under a variety of synthetic loads. Extensive results are presented based on these simulations. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1093/comjnl/36.8.763 | COMPUTER JOURNAL |
Keywords | Field | DocType |
parallel computer,chip | Computer architecture,Architecture,Computer science,Network on a chip,Chip,Integrated circuit design,Logic level,Distributed computing,Embedded system | Journal |
Volume | Issue | ISSN |
36 | 8 | 0010-4620 |
Citations | PageRank | References |
2 | 0.46 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chris R. Jesshope | 1 | 331 | 42.69 |
| Cruz Izu | 2 | 149 | 23.41 |