Name
Abstract | ||
|---|---|---|
A novel tool for full-chip verification is reported for CDM-ESD protection. Until recently, ESD protection has been simulated in device level, leading to the well known limitations on capturing global features such as the power protection circuits and package parasitics. In practice, fatal failures occur due to unexpected discharged paths in multi-power supply chips, which can only be verified by chip-level simulation. Associated with the new concept of macromodelling, hierarchical approach provides effective analysis methodology for mixed-signal chips. The hierarchical approach provides the analysis of chip-level discharging paths and reliability of gate oxide. Simulation results on a CMOS ASIC chip processed in a 0.25-μm technology are in accordance with the measurement data. Scanning electron microscope locates a gate oxide fault as our analysis predicted. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/DAC.2002.1012745 | DAC |
Keywords | Field | DocType |
cmos integrated circuits,gate oxide fault,integrated circuit reliability,cdm-esd protection,cmos asic chip,integrated circuit modelling,power protection circuit,chip-level discharging path,0.25 micron,hierarchical approach,full-chip verification,chip-level simulation,chip-level discharging,macromodel,gate oxide reliability,gate oxide,failure analysis,mixed analogue-digital integrated circuits,vericdf,multi-power supply chip,mixed-signal chip,electrostatic discharge,scanning electron microscopy,effective analysis methodology,new verification methodology,fault location,simulation result,esd protection,package parasitics,charged device failure,protection,hierarchical model,simulation,modeling,scanning electron microscope,cmos technology,packaging,chip,reliability,application specific integrated circuits | Computer science,Electrostatic discharge,Electronic engineering,Chip,CMOS,Gate oxide,Cmos asic,Electronic circuit,Parasitic extraction,Electrical engineering | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-461-4 | 2 |
PageRank | References | Authors |
1.23 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaesik Lee | 1 | 37 | 12.61 |
| Ki-wook Kim | 2 | 98 | 15.76 |
| Sung-Mo Steve Kang | 3 | 1198 | 213.14 |