Paper Info
Title
Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems
Abstract
Multiprocessor systems have been popular for their high performance not only for server markets but also for computing environments for general users. With the increased software complexity, networking overheads in multiprocessor systems are becoming one of the most influential factors in overall system performance. In this paper, we attempt to reduce communication overheads through a data packet compression technique integrating a cache coherence protocol. Here we propose Variable Size Compression (VSC) scheme that compresses or completely eliminates data packets while harmonizing with existing cache coherence protocols. Simulation results show approximately 23% of improvement on average in terms of overall system performance when compared with the most recent compression scheme. VSC also improves performance by 20% on average in terms of cache miss latency.
Year
DOI
Venue
2012
10.1109/DCC.2012.21
DCC
Keywords
Field
DocType
high performance,protocols,cache coherence protocols,multiprocessor system,software complexity,microprocessor chips,cache storage,data packet,data compression,variable size compression scheme,communication overhead,general user,cache coherence protocol,communication overhead reduction,cache coherent multiprocessor systems,computing environments,data packet compression,vsc scheme,overall system performance,recent compression scheme,data packet compression technique,variable size,efficient data packet compression,coherence,cache coherence,system performance,simulation
Cache invalidation,Cache,Computer science,Network packet,Parallel computing,MESI protocol,Multiprocessing,Cache algorithms,Data compression,Cache coherence
Conference
ISSN
ISBN
Citations 
1068-0314
978-1-4673-0715-4
5
PageRank 
References 
Authors
0.46
11
4
Name
Order
Citations
PageRank
Baik Song An1172.37
Manhee Lee2409.04
Ki Hwan Yum332028.13
Eun Jung Kim487367.64