Name
Abstract | ||
|---|---|---|
It is common to use ATPG of scan-based design forhigh fault coverage in LSI testing. However, significantincrease in test cost is caused in accordance withincreasing design complexity. Recent strategies for testcost reduction combine ATPG and BIST techniques.Unfortunately, these strategies have serious constraints.We propose a new method that employs ATE and BISTstructures to apply coded test patterns to LSI circuits.Results obtained using practical circuits show drastic testcost reduction capability of the proposed method. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/VTEST.2003.1197675 | VTS |
Keywords | Field | DocType |
new method,lsi circuit,test cost,scan-based design forhigh fault,lsi testing,bist-aided scan test,test pattern,drastic testcost reduction capability,design complexity,test cost reduction,testcost reduction,automatic test pattern generation,fault coverage,atpg | Automatic test pattern generation,Fault coverage,Logic testing,Computer science,Scan chain,Real-time computing,Electronic engineering,Electronic circuit,Test compression,Reliability engineering,Cost reduction,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-1924-5 | 33 |
PageRank | References | Authors |
1.66 | 15 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takahisa Hiraide | 1 | 43 | 2.97 |
| Kwame Osei Boateng | 2 | 61 | 6.81 |
| Hideaki Konishi | 3 | 51 | 3.24 |
| Koichi Itaya | 4 | 33 | 2.00 |
| Michiaki Emori | 5 | 44 | 3.53 |
| Hitoshi Yamanaka | 6 | 34 | 2.37 |
| Takashi Mochiyama | 7 | 33 | 1.66 |