Paper Info
Title
A high performance adaptive miss handling architecture for chip multiprocessors
Abstract
Chip Multiprocessors (CMPs) mainly base their performance gains on exploiting thread-level parallelism. Consequently, powerful memory systems are needed to support an increasing number of concurrent threads. Conventional CMP memory systems do not account for thread interference which can result in reduced overall system performance. Therefore, conventional high bandwidth Miss Handling Architectures (MHAs) are not well suited to CMPs because they can create severe memory bus congestion. However, high miss bandwidth is desirable when sufficient bus bandwidth is available. This paper presents a novel, CMP-specific technique called the Adaptive Miss Handling Architecture (AMHA). If the memory bus is congested, AMHA improves performance by dynamically reducing the maximum allowed number of concurrent L1 cache misses of a processor core if this creates a significant speedup for the other processors. Compared to a 16-wide conventional MHA, AMHA improves performance by 12% on average for one of the workload collections used in this work.
Year
DOI
Venue
2011
10.1007/978-3-642-24568-8_1
T. HiPEAC
Keywords
Field
DocType
memory bus,conventional cmp memory system,powerful memory system,reduced overall system performance,chip multiprocessors,16-wide conventional mha,adaptive miss handling architecture,performance gain,high performance adaptive,conventional high bandwidth,severe memory bus congestion,sufficient bus bandwidth
Computer science,CPU cache,Parallel computing,Real-time computing,Thread (computing),Bandwidth (signal processing),Memory bus,Cycles per instruction,Multi-core processor,CAS latency,Speedup,Embedded system
Journal
Volume
ISBN
Citations 
4
3-642-24567-6
4
PageRank 
References 
Authors
0.40
19
2
Name
Order
Citations
PageRank
Magnus Jahre122620.50
Lasse Natvig210919.61