Abstract | ||
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Fast Fourier Transform (FFT) algorithms are typically designed to minimize the number of multiplications and additions while maintaining a simple form. Few FFT algorithms are designed to take advantage of hierarchical memory systems, which are easy to include in special-purpose processors, and nearly universal in modem programmable processors. We present a new generalized algorithm, called the cached-FFT which is designed explicitly to operate on a processor with a hierarchical memory system. By taking advantage of a small and fast cache memory, the algorithm enables higher clock frequencies (for special-purpose processor applications), reduced data communication energy, and increased energy-efficiency-since smaller memories require lower energy per access and can be positioned closer to the processor. |
Year | Venue | Keywords |
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2005 | 2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING | fast fourier transform,algorithm design and analysis,generic algorithm,cache memory,fast fourier transforms,energy efficiency,user centered design,energy efficient,frequency |
Field | DocType | ISSN |
Cache-oblivious algorithm,Interleaved memory,Uniform memory access,Shared memory,Computer science,Parallel computing,Distributed memory,Cache-only memory architecture,Fast Fourier transform,Non-uniform memory access | Conference | 1520-6149 |
Citations | PageRank | References |
5 | 0.72 | 3 |
Authors | ||
1 |
Name | Order | Citations | PageRank |
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Bevan M. Baas | 1 | 295 | 27.78 |