Name
Title | ||
|---|---|---|
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors |
Abstract | ||
|---|---|---|
As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 cache with a soft processor that executes the cold code. This paper evaluates the application of the selective depipelining (SDP) technique to ICERs, which greatly reduces both the execution time and energy of irregular computations. SDP enables irregular computations to be expressed as large, fast, low-power combinational blocks. SDP maintains high memory bandwidth by scheduling the many potentially dependent memory operations within these blocks onto a high-frequency, highly-multiplexed coherent memory while scheduling combinational operations at a much lower frequency. SDP is a key enabler for improving the execution properties of irregular computations that are difficult to parallelize. We show that applying SDP to ICERs reduces energy-delay by 2.62脳 relative to ICERs. ICERs with SDP are up to 2.38脳 faster than a soft core processor and reduce energy consumption by up to 15.83脳 for a variety of irregular applications. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/FPL.2011.16 | FPL |
Keywords | Field | DocType |
selective depipelining,irregular code,fpga-based energy-reducing irregular code,dependent memory operation,cold code,energy consumption,high memory bandwidth,irregular application,soft core processor,irregular computation,highly-multiplexed coherent memory,irregular code increase,coprocessors,field programmable gate arrays,logic design,codecs | Logic synthesis,Scheduling (computing),CPU cache,Computer science,High memory,Parallel computing,Field-programmable gate array,Real-time computing,Bandwidth (signal processing),Coprocessor,Energy consumption | Conference |
Citations | PageRank | References |
1 | 0.36 | 20 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jack Sampson | 1 | 398 | 32.45 |
| Manish Arora | 2 | 166 | 11.88 |
| Nathan Goulding-Hotta | 3 | 163 | 10.26 |
| Ganesh Venkatesh | 4 | 274 | 17.97 |
| Jonathan Babb | 5 | 80 | 4.19 |
| Vikram Bhatt | 6 | 77 | 3.78 |
| Steven Swanson | 7 | 1434 | 82.33 |
| Michael Bedford Taylor | 8 | 1707 | 154.51 |