| Q-VR: system-level design for future mobile collaborative virtual reality | 1 | 0.37 | 2021 |
| Pure tensor program rewriting via access patterns (representation pearl) | 1 | 0.35 | 2021 |
| Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures | 2 | 0.39 | 2021 |
| η-LSTM: Co-Designing Highly-Efficient Large LSTM Training via Exploiting Memory-Saving and Architectural Design Opportunities | 0 | 0.34 | 2021 |
| A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. | 2 | 0.37 | 2020 |
| Your Agile Open Source HW Stinks (Because It Is Not a System). | 0 | 0.34 | 2020 |
| ASIC clouds: specializing the datacenter for planet-scale applications | 0 | 0.34 | 2020 |
| BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs | 5 | 0.43 | 2020 |
| Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper | 0 | 0.34 | 2020 |
| A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm | 0 | 0.34 | 2019 |
| Bootstrapping a future of open source, specialized hardware: technical perspective | 0 | 0.34 | 2019 |
| A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS | 0 | 0.34 | 2019 |
| Hiding Intermittent Information Leakage with Architectural Support for Blinking. | 0 | 0.34 | 2018 |
| The BaseJump Manycore Accelerator Network. | 0 | 0.34 | 2018 |
| The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. | 9 | 0.59 | 2018 |
| Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds. | 0 | 0.34 | 2018 |
| The Evolution of Bitcoin Hardware. | 11 | 0.79 | 2017 |
| Specializing a Planet's Computation: ASIC Clouds. | 3 | 0.61 | 2017 |
| Power Side Channels in Security ICs: Hardware Countermeasures. | 1 | 0.36 | 2016 |
| BlackBox: lightweight security monitoring for COTS binaries. | 1 | 0.35 | 2016 |
| DR-SNUCA: An energy-scalable dynamically partitioned cache | 0 | 0.34 | 2013 |
| Bitcoin and the age of bespoke silicon | 19 | 2.98 | 2013 |
| Dark Silicon [Guest editors' introduction]. | 1 | 0.45 | 2013 |
| TimeCube: A manycore embedded processor with interference-agnostic progress tracking. | 1 | 0.35 | 2013 |
| Skadu: Efficient vector shadow memories for poly-scopic program analysis | 0 | 0.34 | 2013 |
| Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse | 67 | 5.10 | 2012 |
| The Kremlin Oracle for Sequential Code Parallelization | 5 | 0.39 | 2012 |
| Kremlin: rethinking and rebooting gprof for the multicore age | 48 | 1.70 | 2011 |
| The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future | 76 | 3.42 | 2011 |
| Efficient complex operators for irregular codes | 18 | 2.95 | 2011 |
| An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors | 1 | 0.36 | 2011 |
| Kremlin: like gprof, but for parallelization | 11 | 0.59 | 2011 |
| Greendroid: Exploring the next evolution in smartphone application processors. | 11 | 0.71 | 2011 |
| Quantification of accuracy and precision of multi-center DTI measurements: A diffusion phantom and human brain study. | 15 | 0.82 | 2011 |
| Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems | 3 | 0.41 | 2011 |
| Unifying manycore and FPGA processing with the RUSH architecture | 1 | 0.35 | 2011 |
| QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores | 64 | 2.77 | 2011 |
| Parkour: parallel speedup estimates for serial programs | 3 | 0.41 | 2011 |
| Kismet: parallel speedup estimates for serial programs | 23 | 1.05 | 2011 |
| Energy and switch area optimizations for FPGA global routing architectures | 1 | 0.35 | 2009 |
| SD-VBS: The San Diego Vision Benchmark Suite | 77 | 2.77 | 2009 |
| Autonomous driving in urban environments: Boss and the Urban Challenge | 349 | 22.87 | 2008 |
| Advancing supercomputer performance through interconnection topology synthesis | 1 | 0.41 | 2008 |
| Fpga Global Routing Architecture Optimization Using A Multicommodity Flow Approach | 1 | 0.37 | 2007 |
| Runtime checking for program verification | 3 | 0.43 | 2007 |
| Scalar Operand Networks | 26 | 1.51 | 2005 |
| Energy characterization of a tiled architecture processor with on-chip networks | 72 | 4.42 | 2003 |
| The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs | 454 | 30.48 | 2002 |
| Value of information based design of control software | 0 | 0.34 | 2002 |
| The RAW benchmark suite: computation structures for general purpose computing | 50 | 9.08 | 1997 |
