Name
Title | ||
|---|---|---|
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing |
Abstract | ||
|---|---|---|
We present a novel algorithm for delay-constrained optimization of combinational logic, extending the state-of-the-art sizing algorithm [1] based on Lagrangian relaxation. We tightly integrate fanout tree construction, buffer insertion/sizing and gate sizing; thereby achieving more optimization than if, they were performed independently. We consider the network in its entirety, thereby taking full advantage of the slacks available on the non-critical paths. We have implemented our algorithm and experimented with it on ISCAS-89 benchmark circuits; the results demonstrate that it is effective as well as fast. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ICCD.2000.878287 | ICCD |
Keywords | Field | DocType |
simultaneous fanout tree construction,fanout tree construction,combinational logic,iscas-89 benchmark circuit,buffer insertion,delay-constrained optimization,gate sizing,delay constrained optimization,full advantage,state-of-the-art sizing algorithm,novel algorithm,lagrangian relaxation,combinational circuits,capacitance,art,logic,circuits,constrained optimization,logic design,constraint optimization,very large scale integration,design optimization | Logic synthesis,Mathematical optimization,Sequential logic,Computer science,Logic optimization,Parallel computing,Combinational logic,Real-time computing,Sizing,Lagrangian relaxation,AND gate,Constrained optimization | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-7695-0801-4 | 0 |
PageRank | References | Authors |
0.34 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| I-Min Liu | 1 | 273 | 18.94 |
| Adnan Aziz | 2 | 1778 | 149.76 |