Name
Abstract | ||
|---|---|---|
This paper presents results of reliability investigation of power VDMOSFET in a Bipolar/CMOS/DMOS technology. In most cases, the mechanisms that degrade these devices are due to mobile and interface charges, incorporated during process steps. Process robustness with efficiency of phosphorus content as gettering agent, in BPSG layer, is performed on VDMOS transistor after controlled sodium incorporation. The reliability tests are performed with classical HTRB on encapsulated components (HTRB at 150degreesC - 1000h) and accelerated HTRB at wafer level (at 300degreesC during 1h). (C) 2003 Elsevier Ltd. All rights reserved. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1016/S0026-2714(03)00317-2 | Microelectronics Reliability |
Field | DocType | Volume |
Robustness (computer science),CMOS,Electronic engineering,Engineering,Transistor | Journal | 43 |
Issue | ISSN | Citations |
9 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y. Rey-Tauriac | 1 | 2 | 2.65 |
| O. de Sagazan | 2 | 0 | 0.34 |
| M. Taurin | 3 | 1 | 1.16 |
| O. Bonnaud | 4 | 13 | 9.82 |