Paper Info
Title
A loop accelerator for low power embedded VLIW processors
Abstract
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performance. However, delivering data to the execution resources in a timely manner remains a major problem that limits ILP. It is particularly significant for embedded systems where memory and power budgets are limited. A distributed address generation and loop acceleration architecture for VLIW processors is presented. This decentralized on-chip memory architecture uses multiple SRAMs to provide high intra-processor bandwidth. Each SRAM has an associated stream address generator capable of implementing a variety of addressing modes in conjunction with a shared loop accelerator.The architecture is extremely useful for generating application specific embedded processors, particularly for processing input data which is organized as a stream. The idea is evaluated in the context of a fine grain VLIW architecture executing complex perception algorithms such as speech and visual feature recognition. Transistor level Spice simulations are used to demonstrate a 159x improvement in the energy delay product when compared to conventional architectures executing the same applications.
Year
DOI
Venue
2004
10.1145/1016720.1016726
CODES+ISSS
Keywords
Field
DocType
vlsi,performance,embedded systems,chip,low power electronics,vliw,embedded system,embedded processor,integrated circuit design,design
Computer science,Very long instruction word,Real-time computing,Very-large-scale integration,Memory architecture,Low-power electronics,Computer architecture,Parallel computing,Static random-access memory,Bandwidth (signal processing),Integrated circuit design,Addressing mode,Embedded system
Conference
ISBN
Citations 
PageRank 
1-58113-937-3
22
1.57
References 
Authors
8
2
Name
Order
Citations
PageRank
Binu K. Mathew116612.25
Al Davis298654.47