Title
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs
Abstract
This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a welltailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.
Year
DOI
Venue
2006
10.1007/978-0-387-34733-2_11
BIOLOGICALLY INSPIRED COOPERATIVE COMPUTING
Keywords
Field
DocType
design methodology,system on chip,work in progress,error detection,fault tolerant
Architecture,Fault coverage,Computer science,Architecture framework,Design methods,Error detection and correction,Embedded system
Conference
Volume
ISSN
Citations 
216
1571-5736
3
PageRank 
References 
Authors
0.43
11
6
Name
Order
Citations
PageRank
Abdelmajid Bouajila1272.95
Andreas Bernauer2384.68
Andreas Herkersdorf370388.32
Wolfgang Rosenstiel41462212.32
Oliver Bringmann558671.36
Walter Stechele636552.77