Name
Abstract | ||
|---|---|---|
An innovative approach for high-level synthesis of digital circuits with semi-concurrent self-checking abilities is introduced, achieving a compromise between redundancy and checking effectiveness. Attention is mainly focused on the data path, described as a general Sequencing Graph including linear paths as well as loops and branches. A reference architecture is defined; a technique allowing to reduce redundancy through resource sharing is then introduced, leading to synthesis of the self-checking architecture. An algorithm is proposed to simultaneously schedule and allocate the resources, while keeping error aliasing as reduced as possible. The desired checking periodicity is guarantee by the algorithm |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/DFTVS.1997.628337 | DFT |
Keywords | Field | DocType |
semi-concurrent error detection,digital circuit,scheduling,data flow graphs,innovative approach,error detection,error aliasing,sequencing graph,resource allocation,algorithm,linear path,redundancy,automatic testing,resource sharing,data paths,reference architecture,general sequencing graph,data path,semi-concurrent self-checking ability,self-checking architecture,high-level synthesis,high level synthesis,digital circuits,fault detection,scheduling algorithm,computer architecture,resource management,concurrent computing | Digital electronics,Computer science,High-level synthesis,Triple modular redundancy,Real-time computing,Error detection and correction,Aliasing,Redundancy (engineering),Reference architecture,Redundancy (information theory),Distributed computing | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-8186-8168-3 | 6 |
PageRank | References | Authors |
0.74 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anna Antola | 1 | 58 | 8.33 |
| Vincenzo Piuri | 2 | 859 | 100.65 |
| Mariagiovanna Sami | 3 | 314 | 39.98 |