Paper Info
Title
A case study on logic diagnosis for System-on-Chip
Abstract
This paper presents an industrial case study on logic diagnosis targeting System-on-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the Effect-Cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
Year
DOI
Venue
2009
10.1109/ISQED.2009.4810303
San Jose, CA
Keywords
Field
DocType
diagnosis accuracy,logic diagnosis,fault model allocation phase,diagnosis approach,critical path,fault model,fault localization phase,fault localization,industrial case study,soc,algebra,system on a chip,system on chip,testing,logic gates,electronics industry,resource management
Resource management,Logic gate,System on a chip,Logic testing,Computer science,Real-time computing,Electronic engineering,Suspect,Critical path tracing,Fault model
Conference
ISBN
Citations 
PageRank 
978-1-4244-2953-0
2
0.43
References 
Authors
16
7
Name
Order
Citations
PageRank
Y. Benabboud141.49
A. Bosio211315.51
P. Girard347841.91
S. Pravossoudovitch468954.12
A. Virazel516923.25
L. Bouzaida620.76
I. Izaute720.76