Name
Abstract | ||
|---|---|---|
This paper investigates implementation techniques for tile-based chip multiprocessors with Globally Asynchronous Locally Synchronous (GALS) clocking styles. These architectures can simplify the physical design flow since they allow focusing on a single processor when designing an entire chip. However, they also introduce challenges to maintain system robustness and scalability. We propose a physical design flow for these architectures, investigate timing issues for robust implementations, and propose methods to take full advantage of their potential scalability. As a design example, we present data from a recently implemented single-chip 6 x 6 tile-based GALS processing array. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICCD.2006.4380812 | ICCD |
Keywords | Field | DocType |
multiprocessing systems,gals clocking styles,globally asynchronous locally synchronous clocking styles,tile-based chip multiprocessors,chip,physical design | Computer architecture,Computer science,Globally asynchronous locally synchronous,Parallel computing,Implementation,Chip,Robustness (computer science),Real-time computing,Physical design,Tile,Scalability,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-6404 E-ISBN : 978-0-7803-9707-1 | 978-0-7803-9707-1 | 8 |
PageRank | References | Authors |
0.78 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiyi Yu | 1 | 81 | 18.24 |
| Bevan M. Baas | 2 | 295 | 27.78 |