Name
Abstract | ||
|---|---|---|
Many techniques have been proposed to reduce the power consumption of multiplexer (MUX) trees. Most of them are performed at the algorithm or circuit level. In this paper, we propose a design method at the register transfer level. In this method, each MUX has its own individual selection signal that is dynamically generated by a dedicated controller. The controller is designed to keep those selection signals as unaltered as possible since only the selection signals lying on the actual output propagation path need to be properly set. Consequently, the switching power in the MUX tree can be reduced. For a 256-to-1 MUX tree with 128-bit input width, the experiment results show that the proposed MUX tree design can reduce 58%~93% power dissipation with negligible area overhead. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746153 | APCCAS |
Keywords | Field | DocType |
logic circuits,word length 128 bit,multiplexing,individual selection signal,dynamic propagation path control,digital signal processing chips,low power multiplexer tree design,256-to-1 multiplexer tree,switching power,switching circuits,power dissipation,design method,register transfer level | Logic gate,Control theory,Dissipation,Computer science,Multiplexer,Electronic engineering,Switching power,Register-transfer level,Multiplexing,Power consumption | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nan-Shing Li | 1 | 0 | 0.34 |
| Juinn-Dar Huang | 2 | 270 | 27.42 |
| Han-Jung Huang | 3 | 1 | 0.72 |