Name
Abstract | ||
|---|---|---|
The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietisy/e89-d.2.853 | IEICE Transactions |
Keywords | Field | DocType |
proposed verification environment,reusable testbench,accelerated verification,effective testbench architecture,functional verification time,conventional co-emulation environment,verification methodology,accelerating verification,non-synthesizable part,hardware accelerator,co-emulation method,software simulator,verification,reuse | Functional verification,Computer science,Reuse,Intelligent verification,Systems design,Random test generator,Hardware acceleration,Systems architecture,Software verification,Embedded system | Journal |
Volume | Issue | ISSN |
E89-D | 2 | 0916-8532 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jungbo Son | 1 | 20 | 4.16 |
| Haewook Choi | 2 | 28 | 7.23 |
| Sin-Chong Park | 3 | 80 | 22.58 |