Name
Abstract | ||
|---|---|---|
In this paper we give a systematic method to design self-exercising (SE) self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-order comparators in the implementation of (k-1)-EC/AUED, (k-1)-EC/d-ED/AUED, (k-1)-EC/d-UED and (k-1)-EC/d-ED/f-UED codes as well as in the design of a fault tolerant cache memory and broadcast networks. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/VTEST.1997.600275 | VTS |
Keywords | Field | DocType |
k-order comparator,self-exercising self testing k-order,k bit,broadcast network,fault tolerant cache memory,systematic method,f-ued code,self testing k-order comparators,k-order comparators,usual equality comparator,combinational circuit,vlsi,combinational circuits,fault tolerant,cache memory | Broadcasting,Comparator,Computer science,CPU cache,Operand,Combinational logic,Real-time computing,Electronic engineering,Fault tolerance,Very-large-scale integration,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-7810-0 | 5 |
PageRank | References | Authors |
0.56 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| X. Kavousianos | 1 | 161 | 12.90 |
| D. Nikolos | 2 | 291 | 31.38 |