Name
Abstract | ||
|---|---|---|
Field-programmable gates arrays (FPGAs) are increasingly used in general-purpose computing platforms to augment microprocessors, enabling runtime loading of coprocessors customized to speed up some applications. Such transmuting coprocessors create new dynamic management problems involving decisions as to when to load a coprocessor, where to place the coprocessor in the FPGA, or which resident coprocessor to replace. We define a transmuting coprocessor problem based on Intel's FSB-FPGA architecture, with attention on communication and memory contention. We develop an online algorithm to manage coprocessor loading, the AG algorithm, which uses aggregated gains to guide coprocessor load, placement, replacement, and wait decisions. Experiments using embedded system applications, for random, biased, and periodic input application sequences, a range of reconfiguration times, and different FPGA types with different numbers of partial reconfigurable regions, demonstrate that the AG algorithm is robust across a variety of situations. The AG algorithm results are within 15% of an unlimited-size FPGA on average, exhibit a small standard deviation, and show a 1.4times speedup versus a static coprocessor loading approach and a 3times speedup over execution on a microprocessor-only solution. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1629911.1630127 | DAC |
Keywords | Field | DocType |
ag algorithm result,fpga coprocessors,acceleration,runtime configuration,resident coprocessor,coprocessor loading,memory contention,microprocessors,dynamic management problems,coprocessing,online algorithm,transmuting coprocessor problem,intel fsb-fpga architecture,coprocessor load,different fpga type,general-purpose computing platforms,dynamic optimization,field-programmable gates arrays,dynamic loading,ag algorithm,online algorithms,static coprocessor loading approach,runtime loading,transmuting coprocessors,fpgas,coprocessors,field programmable gate arrays,computer architecture,field programmable gate array,scheduling algorithm,standard deviation,embedded computing,robustness,embedded system,application specific integrated circuits | Online algorithm,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Dynamic loading,Acceleration,Coprocessor,Dynamic management,Control reconfiguration,Embedded system,Speedup | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-6055-8497-3 | 10 |
PageRank | References | Authors |
0.56 | 10 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen Huang | 1 | 59 | 5.81 |
| Frank Vahid | 2 | 2688 | 218.00 |