Paper Info
Title
Design of ESD power protection with diode structures for mixed-power supply systems
Abstract
The coupling noise immune electrostatic discharge (ESD) protection network is becoming a critical design requirement for preserving the performance of high-speed analog circuits. In this paper, we present a noise-aware design of ESD power protection with diode structures in highly integrated high-speed CMOS ICs. We thoroughly characterize the noise coupled from the ESD power protection network and experimentally verify its generation and impact on the performance of analog circuitry being protected. A noise-aware design technique is proposed to achieve superior noise isolation while improving ESD reliability. The estimation of peak overvoltage on power/ground busses in digital circuits adaptively finds the optimum feature of protection circuits subject to noise constraints. The design is validated with measurements from a test chip fabricated in a 0.18-μm CMOS technology.
Year
DOI
Venue
2004
10.1109/JSSC.2003.820883
Solid-State Circuits, IEEE Journal of
Keywords
DocType
Volume
integrated high-speed cmos ic,cmos integrated circuits,high-speed analog circuits,power bus,esd power protection,digital circuits,diode structures,test chip,mixed-power supply systems,noise-aware design,cmos technology,high-speed integrated circuits,phase locked loops,integrated circuit noise,esd protection network,ground bus,noise isolation,electrostatic discharge,coupling noise immune electrostatic discharge protection,noise constraints,overvoltage protection,esd reliability,peak overvoltage,0.18 micron
Journal
39
Issue
ISSN
Citations 
1
0018-9200
2
PageRank 
References 
Authors
0.52
1
4
Name
Order
Citations
PageRank
J. Lee134450.61
Y. Huh220.52
Peter Bendix3236.39
Sung-Mo Steve Kang41198213.14