A 45nm 37.3GOPS/W heterogeneous multi-core SoC - Citegraph

Paper Info

Title
A 45nm 37.3GOPS/W heterogeneous multi-core SoC

Abstract
A 648 MHz 153.8 mm2 45 nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3 GOPS/W at 1.15 V.

Year	DOI	Venue
2010	10.1109/ISSCC.2010.5434031	ISSCC
Keywords	Field	DocType
cmos soc,cmos integrated circuits,voltage 1.15 v,microprocessor chips,size 45 nm,general purpose cpu,dynamically reconfigurable processor,system-on-chip,matrix processor,clock buffer deactivation,heterogeneous multi-core soc,iron,system on a chip,system on chip,central processing unit	Central processing unit,Video processing,System on a chip,Computer science,Parallel computing,Performance per watt,Multi-core processor,CPU shielding,Automatic parallelization,Data flow diagram	Conference
ISSN	ISBN	Citations
0193-6530	978-1-4244-6033-5	14
PageRank	References	Authors
1.14	5	19

Authors (19 rows)

Cited by (14 rows)

References (5 rows)

Name	Order	Citations	PageRank
Yoichi Yuyama	1	17	3.06
Masanori Ito	2	69	15.48
Yoshikazu Kiyoshige	3	22	2.31
Yusuke Nitta	4	29	5.72
S. Matsui	5	14	1.14
Osamu Nishii	6	59	14.00
Atsushi Hasegawa	7	37	4.40
Makoto Ishikawa	8	23	4.26
Tetsuya Yamada	9	21	3.48
Junichi Miyakoshi	10	78	17.73
Koichi Terada	11	14	1.14
Tohru Nojiri	12	16	2.35
Masashi Satoh	13	14	1.14
Hiroyuki Mizuno	14	28	4.58
Kunio Uchiyama	15	62	15.43
Yasutaka Wada	16	72	11.19
Keiji Kimura	17	120	23.20
Hironori Kasahara	18	285	44.35
Hideo Maejima	19	29	4.74

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