Name
Abstract | ||
|---|---|---|
In this paper we observe that the necessary amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a novel approach to compressed system-on-a-chip testing based on time-multiplexing the tester channels. It is shown how the introduction of a few control channels will enable the sharing of data channels, on which compressed seeds are passed to every embedded core. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to system-on-a-chip devices comprising intellectual property-protected blocks. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TVLSI.2009.2021602 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
on-chip test control,system-on-a-chip testing,test data decompression,data channel,test data,testing process,control channel,embedded core,test data compression,tester channel,soc design,system on a chip,system on chip,chip,logic design,automatic test pattern generation,very large scale integration,hardware,intellectual property protection,frequency,system testing,data transfer,integrated circuit design | Automatic test pattern generation,System on a chip,Computer science,System testing,Electronic engineering,Test data,Modular design,Data compression,Computer hardware,Very-large-scale integration,Embedded system,Scalability | Journal |
Volume | Issue | ISSN |
18 | 8 | 1063-8210 |
Citations | PageRank | References |
4 | 0.42 | 32 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Adam B. Kinsman | 1 | 141 | 10.05 |
| Nicola Nicolici | 2 | 807 | 59.91 |