| Bit-flip detection-driven selection of trace signals. | 0 | 0.34 | 2018 |
| Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-silicon Validation | 1 | 0.40 | 2017 |
| An automated SAT-based method for the design of on-chip bit-flip detectors. | 0 | 0.34 | 2017 |
| On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. | 0 | 0.34 | 2016 |
| Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. | 4 | 0.43 | 2016 |
| Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. | 0 | 0.34 | 2016 |
| Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. | 0 | 0.34 | 2016 |
| Emulation-based selection and assessment of assertion checkers for post-silicon validation | 2 | 0.37 | 2015 |
| SAT Solving using FPGA-based Heterogeneous Computing | 1 | 0.37 | 2015 |
| A methodology for automated design of embedded bit-flips detectors in post-silicon validation | 4 | 0.40 | 2015 |
| Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug | 1 | 0.37 | 2015 |
| On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation | 2 | 0.38 | 2015 |
| A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation | 0 | 0.34 | 2014 |
| A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning | 2 | 0.37 | 2014 |
| FPGA acceleration of enhanced boolean constraint propagation for SAT solvers | 6 | 0.50 | 2013 |
| NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging | 3 | 0.60 | 2013 |
| Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation | 4 | 0.42 | 2013 |
| Automated data analysis techniques for a modern silicon debug environment | 3 | 0.41 | 2012 |
| Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging | 4 | 0.45 | 2012 |
| In-system constrained-random stimuli generation for post-silicon validation | 1 | 0.37 | 2012 |
| Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment | 6 | 0.63 | 2012 |
| On-chip stimuli generation for post-silicon validation | 2 | 0.37 | 2012 |
| Embedded debug architecture for bypassing blocking bugs during post-silicon validation | 5 | 0.40 | 2011 |
| Numerical Data Representations for FPGA-Based Scientific Computing | 8 | 0.57 | 2011 |
| Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research | 2 | 0.40 | 2011 |
| Automated Range and Precision Bit-Width Allocation for Iterative Computations | 6 | 0.46 | 2011 |
| A VLSI architecture and the FPGA prototype for MPEG-2 audio/video decoding | 4 | 0.49 | 2011 |
| A New Algorithm for Post-Silicon Clock Measurement and Tuning | 2 | 0.38 | 2011 |
| Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types | 1 | 0.35 | 2011 |
| On Using Lossy Compression for Repeatable Experiments during Silicon Debug | 3 | 0.40 | 2011 |
| Dynamic binary translation to a reconfigurable target for on-the-fly acceleration | 1 | 0.37 | 2011 |
| A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies | 11 | 0.53 | 2010 |
| Robust design methods for hardware accelerators for iterative algorithms in scientific computing | 4 | 0.42 | 2010 |
| Automated silicon debug data analysis techniques for a hardware data acquisition environment | 5 | 0.48 | 2010 |
| Embedded memory binding in FPGAs | 1 | 0.47 | 2010 |
| Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture | 1 | 0.35 | 2010 |
| A novel optimal single constant multiplication algorithm | 4 | 0.41 | 2010 |
| Time-multiplexed compressed test of SOC designs | 4 | 0.42 | 2010 |
| Automated trace signals selection using the RTL descriptions | 5 | 0.48 | 2010 |
| Post-silicon validation opportunities, challenges and recent advances | 68 | 2.33 | 2010 |
| Real-time lossless compression for silicon debug | 13 | 0.85 | 2009 |
| Computational bit-width allocation for operations in vector calculus | 2 | 0.38 | 2009 |
| Automated data analysis solutions to silicon debug | 18 | 0.78 | 2009 |
| Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug | 69 | 3.16 | 2009 |
| A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications | 1 | 0.46 | 2009 |
| Design-For-Debug For Post-Silicon Validation: Can High-Level Descriptions Help? | 4 | 0.53 | 2009 |
| Resource-Efficient Programmable Trigger Units for Post-Silicon Validation | 12 | 0.69 | 2009 |
| Distributed Embedded Logic Analysis For Post-Silicon Validation Of Socs | 28 | 1.20 | 2008 |
| A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test | 5 | 0.45 | 2008 |
| Power-Aware Testing and Test Strategies for Low Power Devices | 6 | 0.45 | 2008 |
