Name
Abstract | ||
|---|---|---|
Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including VIA, contact, metal, dielectric barriers and low-k dielectrics. Chemical Mechanical Polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1053355.1053364 | SLIP |
Keywords | Field | DocType |
random process variation,induced variation,circuit performance,process variation,etch induced variation,circuit delay,metal topography,transistor process variation,rc delay,potential circuit hazard,testability,yield,signal integrity,chemical mechanical polishing,chip,random process | Computer science,Signal integrity,Power integrity,Voltage drop,Chip,Electronic engineering,RC time constant,Transistor,Interconnection,Electrical engineering,Chemical-mechanical planarization | Conference |
ISBN | Citations | PageRank |
1-59593-033-7 | 0 | 0.34 |
References | Authors | |
1 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. S. Nagaraj | 1 | 86 | 17.37 |