| Moore's Law: another casualty of the financial meltdown? | 1 | 0.35 | 2009 |
| SmartExtract: Accurate Capacitance Extraction for SOC Designs | 1 | 0.36 | 2006 |
| Optimizing Interconnect for Performance in Standard Cell Library | 2 | 0.51 | 2006 |
| Interconnect Process Variations: Theory and Practice | 0 | 0.34 | 2006 |
| The impact of inductance on transients affecting gate oxide reliability | 0 | 0.34 | 2005 |
| Dealing with interconnect process variations | 0 | 0.34 | 2005 |
| BEOL variability and impact on RC extraction | 7 | 0.60 | 2005 |
| Interconnect Modeling for Copper/Low-k Technologies | 1 | 0.37 | 2004 |
| Benchmarks for Interconnect Parasitic Resistance and Capacitance | 11 | 2.00 | 2003 |
| A 600-Mhz Vliw Dsp | 33 | 2.36 | 2002 |
| Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification | 0 | 0.34 | 2002 |
| Interconnect Modeling for Timing, Signal Integrity and Reliability | 0 | 0.34 | 2001 |
| When bad things happen to good chips (panel session) | 0 | 0.34 | 2000 |
| A practical approach to crosstalk noise verification of static CMOS designs | 3 | 0.62 | 2000 |
| Full-Chip Signal Interconnect Analysis for Electromigration Reliability | 0 | 0.34 | 2000 |
| Enabling DIR(Designing-In-Reliability) through CAD Capabilities | 0 | 0.34 | 2000 |
| A practical approach to static signal electromigration analysis | 14 | 4.98 | 1998 |
| Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century | 11 | 2.07 | 1997 |
| A new optimizer for performance optimization of analog integrated circuits | 2 | 0.46 | 1993 |
