Name
Abstract | ||
|---|---|---|
This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2228360.2228543 | DAC |
Keywords | Field | DocType |
long test time,industrial dram arrays,embedded-dram,dram-access frequency,integrated circuit testing,application-specific drams,array layout,pairwise word-line hammering fault detection,alternate hammering test,dram chips,system-on-chip,previous hammering test,application-specific dram,potential fault sites,novel memory test algorithm,industrial case study,fault diagnosis,integrated circuit design,test application,highest dram-access frequency,edram macro,proposed alternate hammering test,memory test algorithm,storage-application soc,hammering test,couplings,capacitors,layout,system on chip | Dram,Pairwise comparison,Application specific,System on a chip,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,eDRAM,Macro,Scalability,Embedded system | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-4503-1199-1 | 8 |
PageRank | References | Authors |
0.73 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rei-Fu Huang | 1 | 165 | 13.15 |
| Hao-Yu Yang | 2 | 27 | 4.88 |
| Mango C.-T. Chao | 3 | 48 | 7.38 |
| Shih-Chin Lin | 4 | 18 | 1.87 |