Name
Title | ||
|---|---|---|
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs |
Abstract | ||
|---|---|---|
H-SCAN[12] was presented as a low overhead design-for-testability strategy which is applicable to RT-level controller-data path circuits. However, from the view-point of practical use, there is a possibility that the area overhead of H-SCAN is larger than that of full-scan.Moreover, H-SCAN is unable to handle many features present in actual designs. In this paper, we propose a modified H-SCAN scheme, called "H-SCAN+", as an improved solution for actual designs. H-SCAN+ consists of several enhancements, including techniques to minimize scan design area overhead, handling of features present in actual designs, and techniques to significantly minimize the running time. We provide comprehensive results of applying H-SCAN+ to several actual RT-level designs. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/TEST.1997.639622 | ITC |
Keywords | Field | DocType |
comprehensive result,actual rt-level design,industrial designs,practical use,improved solution,practical low-overhead rtl design-for-testability,controller-data path circuit,design area overhead,low overhead design-for-testability strategy,modified h-scan scheme,area overhead,actual design,design for testability,sequential circuits,automatic test pattern generation,logic,dft,hardware,industrial design,national electric code | Design for testing,Automatic test pattern generation,Sequential logic,Computer science,Logic testing,Automatic testing,Electronic engineering,Real-time computing,Electronic circuit,National Electrical Code,Ultra large scale integration | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-4209-7 | 11 |
PageRank | References | Authors |
0.74 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshiharu Asaka | 1 | 11 | 1.08 |
| Masaaki Yoshida | 2 | 11 | 0.74 |
| Subhrajit Bhattacharya | 3 | 462 | 36.93 |
| Sujit Dey | 4 | 3067 | 278.74 |