Name
Abstract | ||
|---|---|---|
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/AHS.2006.55 | Istanbul |
Keywords | Field | DocType |
xilinx microblaze soft core,fpga clock frequency,single-chip evolvable hardware system,on-chip evolution,image recognition,xilinx fpga,evolutionary adaptation,suitable hardware architecture,evolutionary algorithm,pentium m system,microblaze system evolves,soft processor core applied,certain face,face recognition,system on a chip,hardware architecture,field programmable gate arrays,computer architecture,digital logic,chip,concurrent computing,evolutionary computation,hardware,system on chip,software performance | MicroBlaze,Evolutionary algorithm,Computer science,Evolvable hardware,Artificial intelligence,Multi-core processor,Computer vision,System on a chip,Parallel computing,Field-programmable gate array,Clock rate,Hardware architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2614-4 | 17 | 0.91 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyrre Glette | 1 | 344 | 41.17 |
| Jim Torresen | 2 | 876 | 96.23 |
| Moritoshi Yasunaga | 3 | 178 | 33.03 |
| Yoshiki Yamaguchi | 4 | 231 | 34.53 |