Moritoshi Yasunaga

Author Info

Name	Affiliation	Papers
MORITOSHI YASUNAGA	Univ Tsukuba, Grad Sch, Doctoral Program Syst & Informat Engn, Tsukuba, Ibaraki 3058573, Japan	53
Collaborators	Citations	PageRank
78	178	33.03
Referers	Referees	References
323	423	218

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100423

Publications (53 rows)

Collaborators (78 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
FPGA-Based Object Detection for Autonomous Driving System	0	0.34	2019
Evolutionary design of high signal integrity interconnection based on eye-diagram	0	0.34	2018
An evolutionary design methodology of printed circuit boards for high-speed VLSIs	0	0.34	2016
A passive equalizer and its design methodology for global interconnects in VLSIs	0	0.34	2016
An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search.	1	0.39	2016
High-Speed Calculation Of Convex Hull In 2d Images Using Fpga	0	0.34	2015
Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines	0	0.34	2015
Digital-signal-waveform improvement on VLSI packaging including inductances	0	0.34	2011
A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems	2	0.44	2010
Development of a novel crossover of hybrid genetic algorithms for large-scale traveling salesman problems	0	0.34	2010
Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging	0	0.34	2010
A visual-inspection system using a self-organizing map	0	0.34	2009
The Segmental-Transmission-Line: Its Design and Prototype Evaluation	2	0.53	2008
Variable-length segmental transmission line and its design guidelines	0	0.34	2008
A reconfigurable VLSI-based double-lens tracking camera	2	0.50	2008
Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera	0	0.34	2008
Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation	0	0.34	2007
A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic	2	0.38	2007
Bio-Inspired Functional Asymmetry Camera System	0	0.34	2007
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA	17	1.07	2007
An Online EHW Pattern Recognition System Applied to Face Image Recognition	14	0.82	2007
A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine	1	0.35	2007
An online EHW pattern recognition system applied to sonar spectrum classification	11	0.72	2007
A bio-inspired tracking camera system	3	0.74	2007
Enhancement Of The Variable-Length-Transmission-Line Design Method For Multi-Point Optimization	2	0.52	2006
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition	17	0.91	2006
Realization of the sound space environment for the radiation-tolerant space craft	1	0.43	2006
Variable Length Segmental-Transmission-Line And Its Parameter Optimization Based On Ga	2	0.45	2005
Finding Transcriptional Regulatory Elements In Dictyostelium Gene Expression	0	0.34	2005
Performance evaluation system for probabilistic neural network hardware.	0	0.34	2004
Performance evaluation system for probabilistic neural network hardware	4	0.77	2004
Multi-Modal Neural Networks For Symbolic Sequence Pattern Classification	0	0.34	2004
A computational approach to detect regulatory elements in Dictyostelium discoideum.	0	0.34	2004
Reconfigurable I/O Interface For Mobile Equipments	2	0.47	2004
A multimodal neural network with single-state predictions for protein secondary structure	0	0.34	2004
Gene finding using evolvable reasoning hardware	6	0.56	2003
Reconfigurable parallel comparation architecture and its application to IP packet filters	1	0.47	2003
Prediction of protein secondary structure by multi-modal neural networks	5	0.60	2002
Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings	27	3.99	2001
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation	2	0.51	2001
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware	15	1.02	2000
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips	3	0.52	2000
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables	0	0.34	2000
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI	0	0.34	2000
A Fast Model-Building Method for Time Series Using Genetic Programming	0	0.34	2000
Sonar spectrum recognition chip designed by evolutionary algorithm	2	0.44	1999
Parallel self-organization map using multiple stimuli	1	0.34	1999
Parallel back-propagation using genetic algorithm: real-time BP learning on the massively parallel computer CP-PACS	0	0.34	1999
Dynamic Optical Topography And The Real-Time Pdp Chip: An Analytical And Synthetical Approach To Higher-Order Brain Functions	0	0.34	1998
Fault-tolerant self-organizing map implemented by wafer-scale integration	3	0.75	1998

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