Name
Abstract | ||
|---|---|---|
Embedded cores are being increasingly used in the designs of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tung and Jon, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/43.992770 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
Keywords | DocType | Volume |
automatic-verification pattern generation (AVPG), design verification, IEEE P1500, port-order fault (POF), SoC, undetected port sequence (UPS) | Journal | 21 |
Issue | ISSN | Citations |
4 | 0278-0070 | 4 |
PageRank | References | Authors |
0.47 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wang Chun-Yao | 1 | 251 | 36.08 |
| Shing-Wu Tung | 2 | 33 | 6.60 |
| Jing-Yang Jou | 3 | 681 | 88.55 |