Name
Abstract | ||
|---|---|---|
Multi- and many-core systems become more and more mainstream and therefore new communication infrastructures like Networks-on-Chip (NoC) and new programming languages like IBM's X10 with its partitioned global address space (PGAS) are introduced. In this paper we present an X10-based simulator, which is capable to simulate the network traffic that occurs inside the X10 program. This holistic approach enables to simulate the functionality and the indicated traffic together, in contrast to pure network simulators where usually only synthetic traffic or traces are used. We explain how the communication overhead is extracted from the X10 run-time and how to simulate the NoC behavior. In experiments we show that the proposed simulator is up to 10 x faster than a comparable SystemC-based simulator and at the same time preserves high accuracy. Furthermore, we present a quality and simulation speed tradeoff by using different simulation modes for a set of real world parallel applications. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2463596.2463606 | M-SCOPES |
Keywords | Field | DocType |
network traffic,heterogeneous architecture,synthetic traffic,pgas programming model,noc behavior,comparable systemc-based simulator,noc simulation,x10-based simulator,proposed simulator,pure network simulator,x10 run-time,indicated traffic,x10 program,network on chip,modeling,parallel programming,simulation | Computer architecture,IBM,Programming paradigm,Computer science,Parallel computing,Network on a chip,SystemC,Real-time computing,Partitioned global address space | Conference |
Citations | PageRank | References |
1 | 0.36 | 12 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sascha Roloff | 1 | 30 | 4.14 |
| Andreas Weichslgartner | 2 | 52 | 7.16 |
| Jan Heisswolf | 3 | 51 | 5.67 |
| Frank Hannig | 4 | 595 | 75.66 |
| Jürgen Teich | 5 | 2886 | 273.54 |