Name
Title | ||
|---|---|---|
An efficient technology mapping algorithm targeting routing congestion under delay constraints |
Abstract | ||
|---|---|---|
Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay-optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1055137.1055166 | ISPD |
Keywords | Field | DocType |
satisfying delay constraint,efficient technology mapping algorithm,probabilistic congestion map,benchmark circuit,delay constraint,nm technology show,technology mapping algorithm,conventional technology mapping,vlsi design,routing congestion,congestion map,logic synthesis,satisfiability | Logic synthesis,Dynamic programming,Mathematical optimization,Dynamic Source Routing,Computer science,Hierarchical routing,Static routing,Algorithm,Probabilistic logic,Electronic circuit,Very-large-scale integration | Conference |
ISBN | Citations | PageRank |
1-59593-021-3 | 7 | 0.52 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rupesh S. Shelar | 1 | 81 | 6.49 |
| Prashant Saxena | 2 | 210 | 25.24 |
| Xinning Wang | 3 | 29 | 2.77 |
| Sachin Sapatnekar | 4 | 4074 | 361.60 |