Paper Info
Title
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections
Abstract
In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.
Year
DOI
Venue
2009
10.1109/VTS.2009.38
VTS
Keywords
Field
DocType
signal integrity fault,abstract model,proposed signal integrity fault,spice-based pattern generation method,test methodology,signal integrity defect,time consuming,high-level signal integrity fault,signal integrity problem,long on-chip interconnections,new high-level signal integrity,fault model,signal transition,signal integrity,fault detection,signal processing,signal analysis,automatic test pattern generation,crosstalk,chip,mathematical model,capacitance,system on a chip,signal detection,noise,process variation,signal generators
Automatic test pattern generation,Signal processing,Computer science,Spice,Signal transition,Fault detection and isolation,Signal integrity,Electronic engineering,Interconnection,Fault model
Conference
ISSN
ISBN
Citations 
1093-0167
978-0-7695-3598-2
0
PageRank 
References 
Authors
0.34
12
4
Name
Order
Citations
PageRank
Sunghoon Chun1315.43
Yong-Joon Kim211813.73
Tae-jin Kim311121.38
Sungho Kang443678.44