Title
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip
Abstract
This paper describes the RTL-to-Iayout implementation of the PACT XPP-III Coarse-Grained Reconfigurable Architecture (CGRA). The implementation activity was strictly based on a hierarchical approach in order to exploit performance optimization at all levels, as well as guarantee maximum scalability and provide a portfolio of IP-blocks that could be reused to build different configurations and embodiments of the same CGRA template. The final result can be seamlessly introduced in any SoC design flow as embedded accelerator. It is designed in STMicroelectronics 90nm GP technology, occupies 42.5 mm2, delivers 13 16-bit GOPS (0.8 GOPS/mW, 10 MOPS/mW) and has a measured max frequency of 150 MHZ, requiring a measured 13 mW/MHz dynamic power, 93 mW static. A silicon prototype was also produced embedding XPP-III in a complex system-on-chip including an ARM processor as system controller as well as different ASIC blocks.
Year
DOI
Venue
2009
10.1109/SOCC.2009.5335665
SOC'09 Proceedings of the 11th international conference on System-on-chip
Keywords
DocType
ISBN
embedded coarse grained architecture,different configuration,rtl-to-iayout implementation,rtl-to-layout implementation,gp technology,implementation activity,pact xpp-iii coarse-grained reconfigurable,cgra template,arm processor,measured max frequency,16-bit gops,different asic block,dynamically reconfigurable computing,integrated circuit layout,system on chip,data mining
Conference
978-1-4244-4467-0
Citations 
PageRank 
References 
5
0.49
2
Authors
13
Name
Order
Citations
PageRank
Fabio Campi122719.26
R. König250.49
Michael Dreschmann3416.58
M. Neukirchner450.49
D. Picard550.49
M. Jüttner650.49
E. Schüler750.49
Antonio Deledda8554.45
D. Rossi950.49
A. Pasini1050.49
M. Hübner1160.87
jurgen becker12516.65
R Guerrieri1312430.04