A multi-core signal processor for heterogeneous reconfigurable computing | 1 | 0.38 | 2009 |
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip | 5 | 0.49 | 2009 |
Implementation of parallel LFSR-based applications on an adaptive DSP featuring a pipelined configurable Gate Array | 3 | 0.42 | 2008 |
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor | 7 | 0.59 | 2008 |
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC | 3 | 0.40 | 2008 |
A dynamically adaptive DSP for heterogeneous reconfigurable platforms | 29 | 1.60 | 2007 |
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture | 7 | 0.56 | 2005 |