Paper Info
Title
Testing, Verification, and Diagnosis in the Presence of Unknowns
Abstract
Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs is important problems in industry. In this paper, we address these problems when portions of the design may be unspecified. Two approaches to solve these problems have been presented: (1) solving Boolean satisfiability under unknown constraints, and (2) a network modification-based solution. Experimental results on constrained equivalence checking, enhancement of error diagnosis resolution for combinational circuits, and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark and industrial circuits.
Year
DOI
Venue
2000
10.1109/VTEST.2000.843854
VTS
Keywords
Field
DocType
fault diagnosis,important problem,equivalence checking,boolean satisfiability,network modification-based solution,ip-based design,industrial circuit,error diagnosis resolution,combinational circuit,automatic test pattern generation,error correction,algorithm design and analysis,circuit analysis,testing,atpg,tires,combinational circuits,boolean functions,process design
Boolean function,Formal equivalence checking,Automatic test pattern generation,Boolean circuit,Computer science,Boolean satisfiability problem,Electronic engineering,Theoretical computer science,Combinational logic,Industrial property,Electronic circuit
Conference
ISBN
Citations 
PageRank 
0-7695-0613-5
33
1.35
References 
Authors
4
6
Name
Order
Citations
PageRank
A. Jain1352.73
V. Boppana2472.89
R. Mukherjee3331.35
J. Jain4422.61
Masayuki Fujita5930103.37
M. Hsiao6382.52