Name
Abstract | ||
|---|---|---|
Signature computation for linear compactors in a BIST environment is a computationally intensive process. In this paper, a fast compaction simulation algorithm is presented which uses superposition and look-up tables. While keeping memory requirements reasonable, this algorithm has a speedup advantage of at least one order of magnitude over traditional algorithms, and offers a threefold speedup over recently published “fast” algorithms. Our algorithm is also applicable to any linear compactor - while existing algorithms are restricted to only one type of compactor. Simulation results comparing the speed and memory requirements of the proposed compaction algorithm to that of existing compaction algorithms are given |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/43.402503 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
fast compaction simulation algorithm,traditional algorithm,linear compactors,proposed compaction algorithm,memory requirement,threefold speedup,simulation result,linear compactor,fast signature computation,compaction algorithm,BIST linear compactors,speedup advantage | Journal | 14 |
Issue | ISSN | Citations |
8 | 0278-0070 | 1 |
PageRank | References | Authors |
0.37 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Lambidonis | 1 | 10 | 1.56 |
| A. Ivanov | 2 | 48 | 5.94 |
| V. K. Agarwal | 3 | 360 | 44.82 |