Name
Title | ||
|---|---|---|
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study |
Abstract | ||
|---|---|---|
NoCs have become a widespread paradigm in the system-on-chip design world, not only for multi-purpose SoCs, but also for application-specific ICs. The common approach in the NoC design world is to separate the design of the interconnection from the design of the processing elements: this is well suited for a large number of developments, but the need for joint application and NoC design is not uncommon, especially in the application-specific case. The correlation between processing and communication tasks can be strong, and separate or trace-based simulations fall often short of the desired precision. In this work, the OMNET++ based JANoCS simulator is presented: concurrent simulation of processing and communication allow cycle-accurate evaluation of the system. The potential of the proposed approach is illustrated through a simple application example. Furthermore, a detailed case study on LDPC and turbo codes parallel decoding is presented. Results analysis illustrates the need for joint simulations and demonstrates the effectiveness of the proposed JANoCS. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/DSD.2013.26 | DSD |
Keywords | Field | DocType |
parallel decoding case study,ldpc,decoder,turbo codes,application specific ic,application-specific ics,integrated circuit interconnections,processing element design,processing element,parallel programming,soc,detailed case study,application simulator,noc design,communication task,joint communication,noc-based custom soc design,turbo,system-on-chip,concurrent processing,multiprocessing systems,noc-based custom socs,concurrent simulation,omnet++ based janocs simulator,integrated circuit design,simulator,common approach,interconnection design,genetic,ldpc code parallel decoding,trace-based simulation,multipurpose soc,noc,parity check codes,network-on-chip,cycle accurate evaluation,noc design world,turbo code parallel decoding,janocs simulator,system-on-chip design world,application-specific case,network on chip | Low-density parity-check code,Computer science,Turbo code,Real-time computing,Turbo,Computer architecture,Simulation,Parallel computing,Network on a chip,Multiprocessing,Integrated circuit design,Decoding methods,Interconnection | Conference |
Citations | PageRank | References |
1 | 0.36 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carlo Condo | 1 | 132 | 21.40 |
| Amer Baghdadi | 2 | 386 | 48.33 |
| Guido Masera | 3 | 640 | 74.10 |