| High-performance low-complexity error pattern generation for ORBGRAND decoding. | 0 | 0.34 | 2021 |
| Sliding Window Polar Codes | 0 | 0.34 | 2021 |
| Fast-SCAN decoding of Polar Codes | 0 | 0.34 | 2021 |
| High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications. | 0 | 0.34 | 2020 |
| On List Decoding of 5G-NR Polar Codes | 0 | 0.34 | 2020 |
| Fast and Efficient Convolutional Accelerator for Edge Computing. | 2 | 0.38 | 2020 |
| Staircase construction with non-systematic polar codes | 0 | 0.34 | 2020 |
| Operation Merging for Hardware Implementations of Fast Polar Decoders | 1 | 0.36 | 2019 |
| Improved Hybrid Design Of Polar Codes And Multi-Kernel Polar Codes | 0 | 0.34 | 2019 |
| Rate-Flexible Fast Polar Decoders. | 1 | 0.35 | 2019 |
| Design and Implementation of a Polar Codes Blind Detection Scheme. | 0 | 0.34 | 2019 |
| Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes. | 4 | 0.47 | 2019 |
| A Multi-Kernel Multi-Code Polar Decoder Architecture. | 2 | 0.44 | 2018 |
| A Convolutional Accelerator for Neural Networks With Binary Weights | 3 | 0.43 | 2018 |
| Memory Management in Successive-Cancellation based Decoders for Multi-Kernel Polar Codes. | 0 | 0.34 | 2018 |
| A Multi-Mode Accelerator for Pruned Deep Neural Networks | 0 | 0.34 | 2018 |
| Design of Polar Codes in 5G New Radio | 6 | 0.44 | 2018 |
| Efficient Operation Scheduling in Successive-Cancellation-based polar decoders | 0 | 0.34 | 2018 |
| A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. | 0 | 0.34 | 2018 |
| Generalized Fast Decoding of Polar Codes. | 0 | 0.34 | 2018 |
| Design and Implementation of a Polar Codes Blind Detection Scheme. | 4 | 0.45 | 2018 |
| An Architecture to Accelerate Convolution in Deep Neural Networks. | 4 | 0.45 | 2018 |
| Decoder Partitioning: Towards Practical List Decoding of Polar Codes. | 5 | 0.47 | 2018 |
| Memory-Efficient Polar Decoders. | 3 | 0.44 | 2017 |
| Blind Detection with Polar Codes. | 10 | 0.77 | 2017 |
| Activation pruning of deep convolutional neural networks. | 1 | 0.35 | 2017 |
| On Error-Correction Performance and Implementation of Polar Code List Decoders for 5G. | 0 | 0.34 | 2017 |
| Implementation of Sparse Superposition Codes | 1 | 0.35 | 2017 |
| Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks. | 0 | 0.34 | 2017 |
| Efficient bit-channel reliability computation for multi-mode polar code encoders and decoders | 1 | 0.35 | 2017 |
| Reduced-memory high-throughput fast-SSC polar code decoder architecture | 3 | 0.42 | 2017 |
| Fast and Flexible Successive-Cancellation List Decoders for Polar Codes. | 15 | 0.72 | 2017 |
| Multi-Mode Inference Engine for Convolutional Neural Networks. | 0 | 0.34 | 2017 |
| Stall Pattern Avoidance In Polynomial Product Codes | 0 | 0.34 | 2016 |
| A Fast Polar Code List Decoder Architecture Based on Sphere Decoding. | 8 | 0.51 | 2016 |
| Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks. | 0 | 0.34 | 2016 |
| Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures | 0 | 0.34 | 2015 |
| Unequal Error Protection of memories in LDPC decoders | 4 | 0.42 | 2015 |
| List Sphere Decoding Of Polar Codes | 1 | 0.39 | 2015 |
| Sparse superposition codes: A practical approach | 4 | 0.42 | 2015 |
| Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders | 1 | 0.40 | 2015 |
| Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding | 0 | 0.34 | 2014 |
| Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced | 0 | 0.34 | 2014 |
| Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications | 1 | 0.35 | 2014 |
| Unified turbo/LDPC code decoder architecture for deep-space communications | 1 | 0.36 | 2014 |
| A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors | 1 | 0.36 | 2014 |
| A joint communication and application simulator for NoC-based SoCs | 0 | 0.34 | 2013 |
| VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture | 28 | 1.01 | 2013 |
| A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study | 1 | 0.36 | 2013 |
| A network-on-chip-based turbo/LDPC decoder architecture | 10 | 0.65 | 2012 |
