Name
Abstract | ||
|---|---|---|
Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1233501.1233645 | ICCAD |
Keywords | Field | DocType |
soft-core programmable processor,soft-core processor,soft-core fpga processor,processor size reduction,soft-core size,share hardware unit,xilinx microblaze coprocessors,hardware unit,custom coprocessors,best custom instantiation,conjoining processor,field programmable gate array,field programmable gate arrays,embedded system,tuning,fpgas,coprocessors,floating point unit,customization | MicroBlaze,Computer architecture,Computer science,Field-programmable gate array,Cycle count,Real-time computing,Soft core,Coprocessor,Electronic circuit,Personalization | Conference |
ISBN | Citations | PageRank |
1-59593-389-1 | 7 | 0.90 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Sheldon | 1 | 56 | 5.42 |
| Rakesh Kumar | 2 | 544 | 39.27 |
| Frank Vahid | 3 | 2688 | 218.00 |
| Dean M. Tullsen | 4 | 4208 | 265.60 |
| Roman Lysecky | 5 | 605 | 60.43 |