Name
Abstract | ||
|---|---|---|
Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ATS.2010.67 | Asian Test Symposium |
Keywords | Field | DocType |
logic bist,test response,new adaptive low shift,test pattern generator,power random test pattern,shift power reduction,shift power consumption,automatic test pattern generation,scan test,built-in self test,existing method,bist,adaptive low shift power,dramatic shift power reduction,low power,scan shift,adjacent test stimulus bit,test coverage loss,logic testing,adaptive low shift power test pattern generator,power control,switches,random testing,computer architecture,industrial design,test coverage,logic gates | Code coverage,Automatic test pattern generation,Logic gate,Computer science,Power control,Electronic engineering,Test pattern generators,Real-time computing,Test compression,Built-in self-test,Power consumption | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-4244-8841-4 | 7 |
PageRank | References | Authors |
0.59 | 15 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Janusz Rajski | 2 | 2460 | 201.28 |