Name
Title | ||
|---|---|---|
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration |
Abstract | ||
|---|---|---|
This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2013.2284651 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS integrated circuits,UHF integrated circuits,UHF oscillators,digital phase locked loops,feedback,jitter,low-power electronics,voltage-controlled oscillators,CMOS process,IL-ADPLL,all-digital PVT calibration,digital phase locked loops,dual-VCO architecture,feedback loop,frequency 1.2 GHz,injection-locked VCO,injection-locked all-digital PLL,low-jitter dual-loop injection locked PLL,power 0.97 mW,power 1.6 mW,size 65 nm,ADPLL,CMOS,FLL,PLL,PVT calibration,all-digital,dual-injection,injection locking,logic gates,logic synthesis,low jitter,low phase noise,low power,small area,small spur,synthesized | Dual loop,Phase-locked loop,Control theory,Computer science,Voltage,CMOS,Voltage-controlled oscillator,Feedback loop,Electronic engineering,Jitter,Low-power electronics | Journal |
Volume | Issue | ISSN |
49 | 1 | 0018-9200 |
Citations | PageRank | References |
29 | 1.67 | 10 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmed Musa | 1 | 52 | 4.50 |
| Wei Deng | 2 | 29 | 1.67 |
| Teerachot Siriburanon | 3 | 149 | 21.47 |
| Masaya Miyahara | 4 | 165 | 32.68 |
| Kenichi Okada | 5 | 497 | 100.11 |
| Akira Matsuzawa | 6 | 465 | 88.10 |