Name
Title | ||
|---|---|---|
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface |
Abstract | ||
|---|---|---|
Among the stacked dies using through silicon via (TSV), data conflictions occur due to process mismatches, which decrease the data valid window and consume unwanted power due to the short circuit current. This paper presents the DLL-based data self-aligner (DBDA), which reduces data conflictions among stacked dies. The stacked dies employing the proposed DBDAs automatically align their data output timings without relying on any control signals from the master die or an extra signal among the stacked die. The DBDA reduces the data confliction time (tDC) due to process, voltage and temperature (PVT) variations from 500 ps to 50 ps and thereby reduces the short current from 3.62 mA to 0.41 mA. The proposed DBDA has two operation modes: the synchronous self-align mode (SSAM), in which the data is aligned in the external clock domain and the asynchronous self-align mode (ASAM). The lock time of DBDA is less than 20 cycles in SSAM. Additionally, the lock detector (LD) and proposed re-calibrator help the DBDA to find the optimal calibration period under temperature variation. They also reduce the calibration current of DBDA by 45.5%. A prototype DBDA implemented in 130 nm CMOS technology dissipates 247 μW for 800 Mb/s/pin. For reduction of the leakage current during the power down mode or the self-refresh mode, this paper proposes a leakage current controller, which reduces the leakage power by 90.5%. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2242251 | J. Solid-State Circuits |
Keywords | Field | DocType |
leakage power,power 247 muw,synchronous self-align mode,cmos integrated circuits,calibration,data valid window,gddr6,tsv interface,pvt variations,short-circuit currents,power down mode,self-refresh mode,leakage currents,ld,power down,asam,size 247 mum,short circuit current,external clock domain,deep power down,synchronous mirror delay (smd),self-aligner,three-dimensional integrated circuits,size 130 nm,data confliction,lock detector,through silicon via (tsv),delay-locked loop (dll),dll-based data self-aligner,data confliction time,dynamic random access memory (dram),cmos technology,time 500 ps to 50 ps,leakage current controller,short current,self-refresh,half period detector,pvt variation,control signals,optimal calibration period,dbda,current 3.62 ma to 0.41 ma,through silicon via interface,delay lock loops,stacked dies,asynchronous self-align mode,ssam,process-voltage and temperature variation,leakage current,detectors | Asynchronous communication,Control theory,Leakage (electronics),Computer science,Voltage,Electronic engineering,CMOS,Short circuit,Through-silicon via,Electrical engineering,Detector | Journal |
Volume | Issue | ISSN |
48 | 3 | 0018-9200 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Soo-Bin Lim | 1 | 6 | 1.33 |
| Hyun-Woo Lee | 2 | 162 | 43.02 |
| Junyoung Song | 3 | 40 | 11.42 |
| Chulwoo Kim | 4 | 397 | 74.58 |