| A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. | 0 | 0.34 | 2022 |
| 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links | 3 | 0.41 | 2021 |
| 12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. | 3 | 0.40 | 2019 |
| A <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math></inline-formula> Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth | 1 | 0.48 | 2019 |
| A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. | 0 | 0.34 | 2019 |
| A Delta Sigma Modulator-Based Spread-Spectrum Clock Generator With Digital Compensation And Calibration For Phase-Locked Loop Bandwidth | 0 | 0.34 | 2019 |
| A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. | 1 | 0.37 | 2018 |
| 29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. | 0 | 0.34 | 2017 |
| A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. | 1 | 0.37 | 2017 |
| A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. | 0 | 0.34 | 2017 |
| A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. | 0 | 0.34 | 2017 |
| A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. | 1 | 0.36 | 2017 |
| A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. | 0 | 0.34 | 2016 |
| A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. | 0 | 0.34 | 2016 |
| 17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces | 5 | 0.57 | 2015 |
| An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator | 0 | 0.34 | 2014 |
| A 7.5-Gb/S Referenceless Transceiver With Adaptive Equalization And Bandwidth-Shifting Technique For Ultrahigh-Definition Television In A 0.13-Mu M Cmos Process | 0 | 0.34 | 2014 |
| 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector | 3 | 0.45 | 2014 |
| A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. | 0 | 0.34 | 2014 |
| A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- CMOS Process | 0 | 0.34 | 2014 |
| A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface | 1 | 0.36 | 2013 |
| A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process | 0 | 0.34 | 2013 |
| Design and implementation of an on-chip permutation network for multiprocessor system-on-chip | 2 | 0.40 | 2013 |
| An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface | 3 | 0.60 | 2013 |
| A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection | 12 | 0.80 | 2013 |
| A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface | 2 | 0.37 | 2012 |
| A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS | 0 | 0.34 | 2012 |
| Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application | 1 | 0.36 | 2009 |
| An architecture for supporting batch query and online service in Very Large Database systems | 1 | 0.38 | 2006 |
