Name
Abstract | ||
|---|---|---|
As the number of instructions executed in parallel increases,superscalar processors will require higher bandwidth fromdata caches. Because of the high cost of true multi-portedcaches, alternative cache designs must be evaluated. Thepurpose of this study is to examine the data cache bandwidthrequirements of high-degree superscalar processors,and investigate alternative solutions. The designs studiedrange from classic solutions like multi-banked caches to morecomplex solutions recently... |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1145/263580.263595 | International Conference on Supercomputing 2006 |
Keywords | Field | DocType |
superscalar processor,data cache | Pipeline burst cache,Cache,Computer science,Parallel computing,Chip,Ranging,Bandwidth (signal processing),Data cache,Superscalar | Conference |
ISBN | Citations | PageRank |
0-89791-902-5 | 27 | 1.47 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toni Juan | 1 | 520 | 41.42 |
| Juan J. Navarro | 2 | 323 | 42.90 |
| Olivier Temam | 3 | 2474 | 148.79 |